   +-----------------------------------------------------------------------+
   |                                                                       |
   | I have noticed that when I mask off interrupts by changing the MR,    |
   | interrupts are still processed for a short period.  Why isn't the new |
   | interrupt mask used immediately when the MR is changed and how long   |
   | does it take for the new mask to be used?                             |
   |                                                                       |
   +-----------------------------------------------------------------------+


There are some situations where the DSP56000/1 instruction pipeline
becomes visible to the programmer.  The instruction pipe has three stages
(fetch, decode, and execute) such that as the current instruction is being
executed, the next instruction is being decoded and the following one is
being fetched.  In addition, an interrupt has two additional control cycles
executed before the fetch cycle.  During these two control cycles, the
interrupt arbitration is done.  Interrupt arbitration means that the interrupt
level is compared against the interrupt mask and the interrupt is either
allowed or disallowed.  Therefore, if the interrupt mask is changed after an
interrupt is arbitrated and before the interrupt is executed, the interrupt
will be executed regardless of what the mask was changed to.  The following
examples show that the previous interrupt mask is in effect for up to four
additional instruction cycles after the interrupt mask is changed.  Note that
all instructions shown in the examples here are one word instructions.  One
two-word instruction may be replaced with two one-word instructions except
where noted. 


Program flow with no interrupts after interrupts are disabled:
         .
         .
        ORI #03,MR     ;disable interrupts
        INST 1
        INST 2
        INST 3
        INST 4
         .
         .

Possible variations in program flow after interrupts are disabled:
 .              .              .              .
 .              .              .              .
ORI #03,MR     ORI #03,MR     ORI #03,MR     ORI #03,MR
IV             INST 1         INST 1         INST1
IV+1           IV             INST 2         INST 2  
INST 1         IV+1           IV             INST 3 <--See note 1
INST 2         INST 2         IV+1           IV 
INST 3         INST 3         INST 3         IV+1
INST 4         INST 4         INST 4         INST 4
 .              .              .              .
 .              .              .              .

Note 1: INST 3 may be executed at that point only if the preceding
instruction (INST 2) was a single-word instruction. 

Note 2: IV = Instruction Vector


The following program flow will not occur:
         .
         .
        ORI #03,MR
        INST 1
        INST 2
        INST 3
        INST 4
     IV
     IV+1
         .
         .


Program flow without interrupts after interrupts are re-enabled:
         .
         .
        ANDI #03,MR    ;enable interrupts
        INST 1
        INST 2
        INST 3
        INST 4
         .
         .

Program flow with interrupts after interrupts are re-enabled:
         .
         .
        ANDI #03,MR     ;Enable interrupts
        INST 1          ;Uninterruptable
        INST 2          ;Uninterruptable
        INST 3          ;Interrupt request appears here
        INST 4          ;Execution of INST 4 occurs here if INST 3 is
	IV              ;  a 1-word instruction
        IV+1
         .
         .
